RIFF BOX JTAG firmware/hardware supports communication with single or multichained TAP controllers. All currently supported cores, according to IEEE 1149.1 Test Access Port standard, put 0b1 data into IR register upon CAPTURE state. Thus it makes possible automatic detection of IR register size of each TAP present on the JTAG chain. In this case IR ‘pre-’ and ‘post-’ stuffing bit sizes are not required to be specified by user and are determined automatically. All is needed is a TAP controller position number of the device user is trying to connect to.

Here are ARM cores currently supported by the RIFF BOX JTAG firmware:
– ARM926
– ARM920T
– ARM1136
– PXA312
– PXA270
– OMAP3x (has TAP Router module)

Supported chipsets based on those ARM cores with RIFF DCC Loader functionality (that is NAND memory operations through custom chip’s NAND controller):
– Intel XScale PXA312;
– Intel XScale PXA270;
– Qualcomm MSM62xx (except MSM6250x group);
– Qualcomm MSM6250x ;
– Samsung S3C2440;
– Samsung S3C6410;
– Broadcomm BCM21xxx;
– OneNAND (not chipset, but still…)

In short, if you have a device in hands which has supported chipset inside and if this chipset’s core belongs to the supported ARM cores list, then you can connect and read/write memory of your device over JTAG link.

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